The present invention relates to the field of integrated circuits, and in particular to that of passive components integrated on die.
In the field of integrated circuits, there is an increasing requirement: to reduce the size taken up by the components, to reduce the fabrication costs, and to introduce new functions.
To achieve these objectives, it is necessary to integrate collectively onto the same analog or digital integrated circuit die an increasing number of components that were previously fabricated separately. There are essentially three categories of such components: circuits called “active” (transistors), components called “passive” (resistors, capacitors, inductors), and, finally, micro-electro-mechanical systems (MEMS) (acoustic filters, radio-frequency switches, variable capacitors).
Passive components and/or MEMS can be integrated independently of transistors, but their monolithic integration with transistors is the most beneficial in terms of compactness and cost. However, this monolithic integration causes a certain number of technological difficulties.
First, the nature of the layers and the treatments necessitated by the fabrication of the passive components are not always readily compatible with fabrication on the active circuits. For example, there exist situations in which the production of a second material after that of a first material in a stack on a silicon wafer necessitates the use of a temperature higher than that above which said first material is degraded unacceptably. This is the case in particular for integrating decoupling capacitors into integrated circuits. These capacitors must store a high electrical charge—the electrical charge is proportional to the capacitance and to the supply voltage, so increasing the capacitance improves the required performance (it will be remembered that the capacitance is proportional to the dielectric constant and to the electrode area and inversely proportional to the thickness of the dielectric of the capacitor).
Capacitors are conventionally produced on the same wafer as transistors. To reduce production costs, it is naturally desirable to use small capacitors. Obtaining the required capacitances using dielectric materials with a dielectric constant that is very high compared to the usual materials (SiO2, Si3N4, Ta2O5, ZrO2 or Al2O3) may then be envisaged.
There exist ferroelectric materials, belonging to the class of perovskites, which have very high dielectric constants (relative constant of several hundred units). Perovskites constitute almost all of the materials investigated for high-capacitance capacitor applications in the required range of dielectric constants (see for example the paper by T. Ayguavives et al. entitled “Physical Properties of (Ba,Sr)TiO3 Thin Films used for Integrated Capacitors in Microwave Applications”, IEEE 2001). The perovskite crystalline phase is usually obtained at temperatures from 600° C. to 700° C. However, these temperatures are incompatible with the aluminum- or copper-based interconnection metal of the transistors. Although certain prior art low-temperature processes use a perovskite (see for example the paper by D. Liu et al. entitled “Integrated Thin Film Capacitor Arrays”, International Conference on High Density Packaging and MCMs, 1999), they in fact relate to a phase in which the perovskite is not pure or is of mediocre structural or microstructural quality, which means that the dielectric constant is very much lower than that of the same material when annealed at a higher temperature.
The standard methods mentioned hereinabove therefore do not really exploit the advantages of perovskites, because the maximum authorized temperature decreases progressively as and when the process steps are carried out, and the main difficulty results from the fact that the placement of a “hot” process material (the dielectric) occurs after that of a “cold” process material (the interconnection metal).
There is nevertheless known in the art a method for heating the dielectric to a temperature higher than the interconnection metals can withstand. It consists in isolating the dielectric from the interconnection metal by means of a thermal protection layer and then annealing the dielectric using a pulsed laser with sufficiently brief pulses for the temperature of the metal to remain lower than the temperature of the dielectric and to remain acceptable, provided that thermal diffusion is relatively low (see for example the paper by P. P. Donohue et al. entitled “Pulse-Extended Excimer Laser Annealing of Lead Zirconate Titanate Thin Films”, proceedings of the 12th International Symposium on Integrated Ferroelectrics, Aachen, Germany, March 2000, published in Integrated Ferroelectrics, vol. 31, pages 285 to 296, 2000). This method is difficult to control, however, because the protective layer remains on the wafer. The protective layer therefore cannot be very thick (it is usually less than 2 μm thick), and it may affect the electrical performance of the devices. The temperature difference between the interconnection metal and the dielectric is therefore limited; in other words, the temperature to which the dielectric may be subjected is limited. Moreover, the stack is subjected to a high thermal gradient during this operation, which can generate a surface temperature that is too high or cause non-homogeneous crystallization of the dielectric or deterioration of materials, such as microcracks, as a result of thermal expansion.
One prior art solution to this temperature problem consists in producing the passive devices incorporating the capacitors on a silicon wafer other than the substrate containing the active components and then connecting the two dies together by wires or by microballs (see for example the paper by R. Heistand et al. entitled “Advances in Passive Integration for C/RC Arrays & Networks with Novel Thin & Thick Film Materials”, 36th Nordic IMAPS conference, Helsinki, 1999). These methods have certain drawbacks, however: wires cannot be used to make short connections between capacitor and transistors, and microball connections may be produced on top of a circuit only once; if the capacitors are made of this material, it is no longer possible to add other functions such as switches or surface wave filters, for example.
To avoid these problems, the production temperature is usually limited to about 450° C., which enables integration of the components in the usual metallizations, or above them, in integrated circuits based on aluminum or copper (see for example the paper by S. Jenei et al. entitled “High-Q Inductors and Capacitors on Si Substrate”, IEEE 2001, or the paper by Bryan C. Hendrix et al. entitled “Low-Temperature Process for High-Density Thin-Film Integrated Capacitors”, International Conference on High-Density Interconnect and Systems Packaging, 2000). Because of this temperature limit, these standard methods are greatly limited in terms of the type of material and the dielectric constants that can be achieved. The required capacitance values are therefore obtained by producing capacitors occupying a large area, which limits the integration possibilities and adds to the cost of the die because of the increased area that is occupied on the silicon wafer.
There is nevertheless known in the art a method for increasing the area of the electrodes without increasing the lateral dimensions of the die (see the paper by F. Roozeboom et al. entitled “High-Value MOS Capacitor Arrays in Ultradeep Trenches in Silicon”, published in Microelectronic Engineering, vol. 53, pages 581 to 584, Elsevier Science 2000). This method consists in exploiting the depth of the substrate to integrate metal oxide semiconductor (MOS) decoupling capacitors by excavating an array of deep narrow trenches in the substrate: a dielectric layer and then an electrode layer are disposed around these trenches—the other electrode of the array of capacitors covers the surface of the substrate. However, apart from the difficulty of producing uniform dielectric layers in the trenches, the use of capacitor arrays in trenches makes planar integration of passive components with active components difficult.
More generally, a second difficulty arising from the monolithic integration of passive components or MEMS with transistors is that it is not possible to exploit the vertical dimension to improve the characteristics or the compactness of the passive components.
A third difficulty to which the monolithic integration of passive components or MEMS with transistors gives rise is that the type of substrate used for the active circuits disturbs the characteristics of the passive components.
For example, the substrates used for CMOS or BICMOS circuits have conductivities of the order of 10 Ω.cm at most. The currents induced in these substrates by the inductors or conductive lines cause high losses and thereby reduce the quality factors of these structures (high inductance, high resonant frequency, low stray capacitance).
A first prior art solution consists in eliminating a portion of the substrate under the areas that are to receive the inductors and conductive lines (see for example U.S. Pat. No. 5,539,241). A second prior art solution consists in making the substrate insulative under the areas that are to receive the inductors and conductive lines (see for example the paper by H.-S. Kim et al. entitled “A Porous-Si-based Novel Isolation Technology for Mixed-Signal Integrated Circuits”, Symposium on VLSI Technology, 2000). A third solution is disclosed in U.S. Pat. No. 6,310,387—the underlying conductive layers are structured by producing a large number of small conductive areas in a checkerboard pattern that are separated from each other by an insulator and are not grounded. These areas serve as shielding because, in operation, low eddy currents are produced therein that prevent the magnetic field penetrating as far as the substrate; these areas are small enough to prevent these eddy currents inducing in the inductors a magnetic flux opposite to the required flux.
However, these various techniques are complex to use, may compromise the robustness of the integrated circuit and make the placement of active components difficult.
Finally, a difficulty raised specifically by the monolithic integration of MEMS with transistors is that it is necessary to add a cover to protect the mechanical components, without interfering with their operation. One prior art solution consists in bonding a silicon wafer of the same diameter as the wafer on which the circuits have been produced (see for example the paper by H. Tilmans et al. entitled “Zero-Level Packaging for MEMS or MST Devices: the IRS Method”, mstnews 1/00). This technology is relatively costly because it is necessary to add to the cost of the supplementary substrate the cost of bonding, the cost of thinning and the cost of local etching to obtain access to the output electrical contacts on the surface of the circuit, and all of this is needed only to provide protection by means of a cover.